Meta is hiring ASIC Emulation Engineers within our Infrastructure organization to help build large, complex ASICS in machine learning, video transcoding, network acceleration. We are looking for talented individuals with deep experience in HW emulation and prototyping required to build successful world-class SOC and IP for data center applications.
- Develop and drive HW emulation and EDA vendor strategy for Infrastructure SOCs.
- Drive efficiency and productivity improvements in emulation model builds and HW utilizations.
- Collaborate with XFN partners in Enterprise Engineering and DC SiteOps on long term HW capacity planning.
- Partner with internal XFN teams, understand their use models, and drive for better end user experience with emulation HW usage.
- Drive productivity improvements in emulation tools, workflows and infrastructure in collaboration with XFN partners on reliability, debug, runtime, and data analysis of results.
- Partner with Emulation HW and EDA vendors and drive roadmap alignment and influence industry trends and product features.
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
- 12+ years experience with current emulation technologies and methods, including simulation acceleration, in-circuit emulation, speed bridges, virtual prototyping, hybrid methods.
- Track record of ‘first-pass success’ in ASIC where emulation is one of the key validation tools.
- Understanding of compilation and build flow with experience building images from scratch with necessary design modifications to adapt to emulation.
- Experience managing multiple design releases and working with cross functional teams to support and debug customer issues.
- Experience with EDA tools and scripting languages used to build tools and flows for complex emulation environments.
- Experience interfacing with the design, verification, validation and software development teams and understand their needs from an emulation perspective.
- Experience with verification, SoCs or similar designs.
- Experience in architecting emulation systems for various design scales (IP blocks, SOC, multi-chip system) with an understanding of tradeoffs between performance and ease of debug.
- Experience with SystemVerilog and C++ to model RTL components and transactors.
- Experience with post-silicon bringup, debug and reproducing issues on emulator.
- Experience with Palladium & Protium or equivalent tools.
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